1. Field of the Invention
The present invention relates to integrated circuits, and more specifically to integrated circuits having output buffers.
2. Description of Related Art
In conventional CMOS output buffers, bouncing during level switching is caused by a combination of reactive components such as the buffer's output capacitance and load and the reactance of the inductive case, the leads, the bondings, and the related solderings. Because the resistance of the MOS output transistors is usually insufficient to satisfactorily dampen such bouncing, there is an increase in the current that is injected into the PMOS and NMOS circuit elements and an increase in the switching noise.
Further, in devices that are suitable for audio-radio applications, additional problems are caused because the oscillations can propagate to other circuits (e.g., multipliers, demodulators, oscillators, and phase-locked loops) that operate at high frequencies. As a result, undesired effects can be caused by reactive phenomena inherent in the structure that includes the buffer, connection pad, and bonding. Additionally, due to inductive leads, buffers using uncontrolled fast switching can generate oscillations in output signals so as to cause severe timing errors in the downstream circuits.
To overcome such problems, a circuit designer must take the measures necessary to correctly buffer the signals. When there is a need to charge high capacities, suitable techniques such as a slew rate control must be used in the driving buffers. For example, U.S. Pat. No. 5,121,000 discloses a CMOS output buffer circuit that has an output signal with low bouncing and a feedback circuit including a capacitor. The capacitor acts substantially as a damping factor for the bouncing and control is only applied on the pull-down transistor.
Additionally, U.S. Pat. No. 5,311,077 discloses an output buffer circuit in which slew rate control is used to substantially maintain a constant charge and discharge current independent of temperature conditions and the supply voltage. The circuit is divided into two branches that can individually charge and discharge the output stage gates with a constant current. The switching of the circuit is only controlled by input signal variations so no control is applied on the output signal status. Further, the signal is obtained by a hybrid technique that is quite complex to implement.
U.S. Pat. No. 5,619,147 also discloses a CMOS output buffer circuit with slew rate control. The circuit has a feedback circuit connected to the output to control the variation rate of the output signal during the rising and falling edges of the signal. In particular, the feedback circuit includes a capacity and a differential pair of MOS transistors. By appropriately sizing the capacity and the aspect factors of the MOS transistors, both the rising and falling edges can be set up according to desired noise characteristics. However, the buffer circuitry is difficult to implement. Careful design of the MOS transistors is required because the circuit is based on a time constant RC that results from the sizing of the MOS transistors. Thus, the circuit design is not very flexible.